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19-4041; Rev 0; 2/08
KIT ATION EVALU BLE AVAILA
1.2MHz Low-Cost, High-Performance Chargers
General Description Features
High Switching Frequency (1.2MHz) Controlled Inductor Current-Ripple Architecture Reduced BOM Cost Small Inductor and Output Capacitors 0.4% Accurate Charge Voltage 2.5% Accurate Input-Current Limiting 3% Accurate Charge Current Single-Point Compensation Monitor Outputs for 2.5% Accurate Input Current Limit 2.5% Battery Discharge Current (MAX17015 only) AC Adapter Detection Analog/PWM Adjustable Charge-Current Setting Battery Voltage Adjustable for 3 and 4 Cells (MAX17005) or 2 and 3 Cells (MAX17006) Adjustable Battery Voltage (4.2V to 4.4V/Cell) Cycle-by-Cycle Current Limit Battery Short-Circuit Protection Fast Response for Pulse Charging Fast System-Load-Transient Response Programmable Charge Current < 5A Automatic System Power Source Selection with n-Channel MOSFET Internal Boost Diode +8V to +26V Input Voltage Range
MAX17005/MAX17006/MAX17015
The MAX17005/MAX17006/MAX17015 are high-frequency multichemistry battery chargers. These circuits feature a new high-frequency current-mode architecture that significantly reduces component size and cost*. The charger uses a high-side MOSFET with n-channel synchronous rectifier. Widely adjustable charge current, charge voltage, and input current limit simplify the construction of highly accurate and efficient chargers. The charge voltage and charge current are set with analog control inputs. The charge current setting can also be adjusted with a PWM input. High-accuracy current-sense amplifiers provide fast cycle-by-cycle current-mode control to protect against short circuits to the battery and respond quickly to system load transients. In addition, the charger provides a high-accuracy analog output that is proportional to the adapter current. In the MAX17015, this current monitor remains active when the adapter is absent to monitor battery discharge current. The MAX17005 charges three or four Li+ series cells, and the MAX17006 charges two or three Li+ series cells. The MAX17015 adjusts the charge voltage setting and the number of cells through a feedback resistordivider from the output. All variants of the charger can provide at least 4A of charge current with a 10m sense resistor. The charger utilizes a charge pump to control an n-channel adapter selection switch. The charge pump remains active even when the charger is off. When the adapter is absent, a p-channel MOSFET selects the battery. The MAX17005/MAX17006/MAX17015 are available in a small, 4mm x 4mm x 0.8mm 20-pin, lead-free TQFN package. An evaluation kit is available to reduce design time.
Ordering Information
PART MAX17005ETP+ MAX17006ETP+ MAX17015ETP+ TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 20 Thin QFN (4mm x 4mm) 20 Thin QFN (4mm x 4mm) 20 Thin QFN (4mm x 4mm) PKG CODE T2044-3 T2044-3 T2044-3
Applications
Notebook Computers Tablet PCs Portable Equipment with Rechargeable Batteries
+Denotes a lead-free package.
*Patent pending.
Pin Configuration and Minimal Operating Circuit appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
ABSOLUTE MAXIMUM RATINGS
DCIN, CSSP, CSSN, BATT, CSIN, CSIP, ACOK, LX to AGND .......................................................-0.3V to +30V BST to LDO.............................................................-0.3V to +30V CSIP to CSIN, CSSP to CSSN .............................. -0.3V to +0.3V IINP, FB, ACIN to AGND.............................-0.3V to (VAA + 0.3V) VAA, LDO, ISET, VCTL, CC to AGND .......................-0.3V to +6V DHI to LX ....................................................-0.3V to (BST + 0.3V) BST to LX..................................................................-0.3V to +6V DLO to PGND ............................................-0.3V to (LDO + 0.3V) PGND to AGND .................................................... -0.3V to +0.3V Continuous Power Dissipation (TA = +70C) 16-Pin TQFN (derate 16.9mW/C above +70C)....1349.1mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER CHARGE-VOLTAGE REGULATION 2 cells, V VCTL = GND (for MAX17006) 3 cells, VVCTL = VAA (for MAX17005 and MAX17006) Battery Regulation-Voltage Accuracy 4 cells, V VCTL = GND (for MAX17005) FB accuracy using FB divider (for MAX17015) (Note 1) FB Input Bias Curent 2 cells (for MAX17006), 4 cells (for MAX17005) VCTL Range 3 cells (for MAX17005 and MAX17006) VCTL Gain VCTL Input Bias Current CHARGE-CURRENT REGULATION ISET Range ISET Full-Scale Setting ISET = 1.4V ISET = 99.9% duty cycle VISET = VAA/4 or ISET = 99.9% duty cycle VBATT = 1V to 16.8V Trickle Charge-Current Accuracy Charge-Current Gain Error Charge-Current Offset Error BATT/CSIP/CSIN Input Voltage Range ISET Power-Down Mode Threshold ISET falling ISET rising VISET = VAA/6 or ISET = 66.7% duty cycle VISET = VAA/80 or ISET = 5% duty cycle Based on VISET = VVAA/4 and VISET = V VAA/80 Based on VISET = VVAA/4 and VISET = V VAA/80 58.2 -3 38.2 -4.5 1.4 -52 -2 -1.4 0 21 33 26 40 3 40 0.0 80 60 60 61.8 +3 41.8 +4.5 4.6 +52 +2 +1.4 24 31 47 VAA/2 V mV mV % mV % mV % % mV V mV VCELL/VVCTL VVCTL = GND and VCTL = VAA VAA/2 +0.2 5.85 -1 6 VAA 6.15 +1 V/V A 8.3664 12.549 16.733 2.0916 -1 0.0 8.40 8.4336 V 12.60 12.651 16.80 16.867 2.1 2.1084 +1 VAA/2 -0.2 V A CONDITIONS MIN TYP MAX UNITS
Full-Charge Current Accuracy (CSIP to CSIN)
2
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1.2MHz Low-Cost, High-Performance Chargers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER ISET Input Bias Current ISET PWM Threshold ISET Frequency ISET Effective Resolution INPUT-CURRENT REGULATION Input Current-Limit Threshold CSSN Input Bias Current CSSP/CSSN Input-Voltage Range IINP Transconductance IINP Accuracy SUPPLY AND LINEAR REGULATOR DCIN Input Voltage Range DCIN Undervoltage-Lockout (UVLO) Trip-Point DCIN + CSSP + CSSN Quiescent Current DCIN falling DCIN rising Adapter present (Note 2) Adapter absent (Note 2) VBATT = 16.8V Adapter absent (Note 2) Charger shutdown (Note 2) 5.15 3.2 I VAA = 50A VAA falling 2.058 10 -1 V ACOK = 0.4V, VACIN = 1.5V V ACOK = 5.5V, VACIN = 2.5V 6 1 4.18 8 7.9 8.1 8.7 3 30 10 10 200 5.35 100 4.1 4.20 3.1 2.1 20 8.9 6 50 20 20 500 5.55 200 5.0 4.22 3.9 2.142 30 +1 V mV V V V V mV A mA A A 26 V V mA A VCSSP - VCSSN = 60mV VCSSP - VCSSN = 60mV, VIINP = 0V to 4.5V VCSSP - VCSSN = 35mV VCSSP - VCSSN Adapter present 58.5 -2.5 -0.1 8.0 2.66 -2.5 -2.5 2.8 60 61.5 +2.5 +0.1 26.0 2.94 +2.5 +2.5 mV % A V A/mV % f PWM = 3.2MHz VISET = 3V CSSN = BATT, VISET = 5V Rising Falling CONDITIONS MIN -0.2 -0.2 0.8 0.128 8 500 TYP MAX +0.2 +0.2 2.4 UNITS A V kHz Bits
MAX17005/MAX17006/MAX17015
BATT + CSIP + CSIN + LX Input Current LDO Output Voltage LDO Load Regulation LDO UVLO Threshold REFERENCES VAA Output Voltage VAA UVLO Threshold ACIN ACIN Threshold ACIN Threshold Hysteresis ACIN Input Bias Current ACOK ACOK Sink Current ACOK Leakage Current
VBATT = 2V to 19V, adapter present (Note 2) 8.0V < VDCIN < 26V, no load 0 < ILDO < 40mA
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1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SWITCHING REGULATOR DHI Off-Time K Factor Sense Voltage for Minimum Discontinuous Mode Ripple Current Zero-Crossing Comparator Threshold Cycle-by-Cycle Current-Limit Sense Voltage DHI Resistance High DHI Resistance Low DLO Resistance High DLO Resistance Low ADAPTER DETECTION Adapter Absence-Detect Threshold Adapter Detect Threshold Adapter Switch Charge-Pump Frequency Adapter Switch Charge-Pump Refresh Pulse VDCIN - VBATT, VDCIN falling VDCIN - VBATT, VDCIN rising Charger Shutdown DLO DHI +70 +360 180 0.04 0.07 +120 +420 200 0.1 0.15 +170 +580 220 0.20 0.30 mV mV Hz s VDCIN = 19V, VBATT = 10V VCSIP - VCSIN VCSIP - VCSIN VCSIP - VCSIN IDLO = 10mA IDLO = -10mA IDLO = 10mA IDLO = -10mA 105 0.029 0.030 10 10 110 1.5 0.8 3 3 115 3 1.75 6 7 0.041 s/V mV mV mV CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER CHARGE-VOLTAGE REGULATION 2 cells, V VCTL = GND (for MAX17006) 3 cells, V VCTL = VAA (for MAX17005 and MAX17006) 4 cells, V VCTL = GND (for MAX17005) FB accuracy using FB divider (for MAX17015) (Note 1) 2 cells (for MAX17006), 4 cells (for MAX17005) VCTL Range 3 cells (for MAX17005 and MAX17006) VCTL Gain VCELL/VVCTL VAA/2 + 0.2 5.85 VAA 6.15 V/V 8.366 12.549 16.73 2.091 0.0 8.433 12.651 16.86 2.108 VAA/2 - 0.2 V V CONDITIONS MIN TYP MAX UNITS
Battery Regulation-Voltage Accuracy
4
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1.2MHz Low-Cost, High-Performance Chargers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER CHARGE-CURRENT REGULATION ISET Range Full Charge-Current Accuracy (CSIP to CSIN) VISET = VAA/4 or ISET = 99.9% duty cycle V = VAA/6 or VBATT = 1V to 16.8V ISET ISET = 66.7% duty cycle VISET = VAA/80 or ISET = 5% duty cycle Based on VISET = VVAA/4 and VISET = V VAA/80 Based on VISET = VVAA/4 and VISET = V VAA/80 ISET falling ISET rising Rising Falling 0.8 0.128 58.2 -3 -2 8.0 VCSSP - VCSSN = 60mV VCSSP - VCSSN = 60mV, VIINP = 0V to 4.5V VCSSP - VCSSN = 35mV 2.66 -2.5 -2.5 8 DCIN falling DCIN rising Adapter present (Note 2) Adapter absent (Note 2) VBATT = 16.8V Adapter absent (Note 2) Charger shutdown (Note 2) 5.15 3.2 7.9 8.9 6 50 20 20 500 5.55 200 5.0 V mV V A 500 61.8 +3 +2 26.0 2.94 +2.5 +2.5 26 0.0 57.5 -4.2 38 -5 1.4 -52 -2 -1.4 0 21 33 VAA/2 62.5 +4.2 42 +5 4.6 +52 +2 +1.4 24 31 47 2.4 V mV % mV % mV % % mV V mV V kHz mV % A V A/mV % CONDITIONS MIN TYP MAX UNITS
MAX17005/MAX17006/MAX17015
Trickle Charge-Current Accuracy Charge-Current Gain Error Charge-Current Offset Error BATT/CSIP/CSIN Input Voltage Range ISET Power-Down Mode Threshold ISET PWM Threshold ISET Frequency INPUT-CURRENT REGULATION Input Current-Limit Threshold CSSN Input Bias Current CSSP/CSSN Input-Voltage Range IINP Transconductance IINP Accuracy SUPPLY AND LINEAR REGULATOR DCIN Input-Voltage Range DCIN UVLO Trip-Point DCIN + CSSP + CSSN Quiescent Current VCSSP - VCSSN Adapter present
V V mA A
BATT + CSIP + CSIN + LX Input Current LDO Output Voltage LDO Load Regulation LDO UVLO Threshold
VBATT = 2V to 19V, adapter present (Note 2) 8.0V < VDCIN < 26V, no load 0 < ILDO < 40mA
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1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDCIN = VCSSP = VCSSN = 19V, VBATT = VCSIP = VCSIN = 16.8V, VVCTL = VAA, VISET = 1V, TA = -40C to +85C, unless otherwise noted.)
PARAMETER REFERENCES VAA Output Voltage VAA UVLO Threshold ACIN ACIN Threshold ACIN Threshold Hysteresis ACOK ACOK Sink Current SWITCHING REGULATOR DHI Off-Time K Factor Cycle-by-Cycle Current-Limit Sense Voltage DHI Resistance High DHI Resistance Low DLO Resistance High DLO Resistance Low ADAPTER DETECTION Adapter Absence-Detect Threshold Adapter Detect Threshold Adapter Switch Charge-Pump Frequency Adapter Switch Charge-Pump Refresh Pulse DLO DHI VDCIN - VBATT, VDCIN falling VDCIN - VBATT, VDCIN rising +70 +320 180 0.04 0.07 +170 +620 220 0.2 0.3 mV mV Hz s VDCIN = 19V, VBATT = 10V VCSIP - VCSIN IDLO = 10mA IDLO = -10mA IDLO = 10mA IDLO = -10mA 0.029 105 0.041 115 3 1.75 6 7 s/V mV V ACOK = 0.4V, VACIN = 1.5V 6 mA 2.058 10 2.142 30 V mV I VAA = 50A VAA falling 4.18 4.22 3.9 V V CONDITIONS MIN TYP MAX UNITS
Note 1: Accuracy does not include errors due to external resistance tolerances. Note 2: Adapter present conditions are tested at VDCIN = 19V and VBATT = 16.8V. Adapter absent conditions are tested at VDCIN = 16V, VBATT = 16.8V.
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1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
Typical Operating Characteristics
(Circuit of Figure 1, adapter = 19V, battery = 10V, ISET = 1.05V, VCTL = GND, TA = +25C, unless otherwise noted.)
IINP DC ERROR vs. SYSTEM CURRENT
MAX17005 toc01
IINP ERROR vs. SYSTEM CURRENT
MAX17005 toc02
ISET PWM DUTY-CYCLE CHANGE
MAX17005 toc03
10 8 6 IINP ERROR (%) 4 2 0 -2 -4 -6 -8 -10 0 1 2 3 4 5 SYSTEM CURRENT (A)
10 8 6 IINP ERROR (%) 4 2 0 -2 -4 -6 -8 -10 0 VBATT = 12.6V VBATT = 8.4V VBATT = 16.8V
3.0 2.5 2.0 1.5 1.0 0.5 0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 SYSTEM CURRENT (A)
CHARGE-CURRENT ERROR (%)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 DUTY CYCLE
ISET PWM DUTY-CYCLE CHANGE
MAX17005 toc04
ISET PWM FREQUENCY SWEEP
MAX17005 toc05
BATTERY VOLTAGE-SETTING ERROR
MAX17005 toc06
3.5 3.0 CHARGE CURRENT (A) 2.5 2.0 1.5 1.0 0.5 0 0
3.0 2.5 2.0 1.5 1.0 0.5 0 DUTY CYCLE = 25%
0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6
CHARGE-CURRENT ERROR (%)
DUTY CYCLE = 75%
BATTERY VOLTAGE ERROR (%)
10 20 30 40 50 60 70 80 90 100 DUTY CYCLE
0
100 200 300 400 500 600 700 800 FREQUENCY (kHz)
0
0.5 1.0 1.5 2.0 2.5 3.0 VCTL (V)
3.5 4.0 4.5
SYSTEM LOAD TRANSIENT
MAX17005 toc07
EFFICIENCY vs. CHARGE CURRENT
SYSTEM CURRENT 5A/div EFFICIENCY (%) 95 90 85 80 75 70 65 60 4 CELLS 2 CELLS 3 CELLS
MAX17005 toc08
100
CHARGING CURRENT 5A/div INDUCTOR CURRENT 5A/div 200s/div
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
CHARGE CURRENT (A)
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1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
Typical Operating Characteristics (continued)
(Circuit of Figure 1, adapter = 19V, battery = 10V, ISET = 1.05V, VCTL = GND, TA = +25C, unless otherwise noted.)
LDO LOAD REGULATION
MAX17005 toc09
LDO LINE REGULATION
MAX17005 toc10
VAA LOAD REGULATION
4.204 4.203 VAA VOLTAGE (V) 4.202 4.201 4.200 4.199 4.198
MAX17005 toc11
5.50
5.50
4.205
5.45 LDO VOLTAGE (V) LDO VOLTAGE (V)
5.45
5.40
5.40
5.35
5.35
4.197 4.196
5.30 0 5 10 15 20 25 30 35 40 LDO CURRENT (mA)
5.30 8 10 12 14 16 18 20 22 24 26 INPUT VOLTAGE (V)
4.195 0 0.2 0.4 0.6 0.8 1.0 LOAD CURRENT (mA)
VAA vs. TEMPERATURE
MAX17005 toc12
HIGH-SIDE MOSFET OFF-TIME AND SWITCHING FREQUENCY vs. BATTERY VOLTAGE
1.6 VIN = 20V SWITCHING FREQUENCY (MHz) 5 SWITCHING FREQUENCY 1.0 0.8 0.6 0.4 0.2 0 HIGH-SIDE MOSFET OFF-TIME 1 0 18 4 3 2 1.2 HIGH-SIDE MOSFTE OFF-TIME (s) 1.4
MAX17005 toc13
4.2005 4.2000 4.1995 VAA (V) 4.1990 4.1985 4.1980 4.1975 4.1970 4.1965 -60 -40 -20 0 20 40 60 80
6
100
0
2
4
6
8
10
12
14
16
TEMPERATURE (C)
BATTERY VOLTAGE (V)
ADAPTER CURRENT vs. ADAPTER VOLTAGE
MAX17005 toc14
BATTERY LEAKAGE
350 300 250 200 150 100 50 0
MAX17005 toc15
ADAPTER REMOVAL
MAX17005 toc16
1.6 1.4 ADAPTER CURRENT (mA) 1.2 1.0 0.8 0.6 0.4 0.2 0 0 5 10 15
400 BATTERY LEAKAGE CURRENT (A)
5.00V 5.00V 5.00V
20
0
2
4
6
8
10 12 14 16 18 20
200ms/div
ADAPTER VOLTAGE (V)
BATTERY VOLTAGE (V)
8
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1.2MHz Low-Cost, High-Performance Chargers
Pin Description
PIN 1 2 3 4 5 6 7 8 9 NAME DCIN AGND CSIP CSIN IINP BATT ACOK CSSP CSSN Analog Ground Output Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN. Output Current-Sense Negative Input Input Current-Monitor Output. IINP sources the current proportional to the current sensed across CSSP and CSSN. The transconductance from (CSSP - CSSN) to IINP is 2.8A/mV. See the Analog Input Current-Monitor Output section to configure the current monitor for a particular gain setting. Battery Voltage Feedback Input AC Detect Output. This open-drain output is high impedance when ACIN is lower than VAA/2. Connect a 10k pullup resistor from LDO to ACOK. Input Current Sense for Positive Input. Connect a current-sense resistor from CSSP to CSSN. Input Current-Sense Negative Input Dual ModeTM Input for Setting Maximum Charge Current. ISET can be configured either with a resistor voltage-divider or with a PWM signal from 128Hz to 500kHz. If there is no clock edge within 20ms, ISET defaults to analog input mode. Pull ISET to GND to shut down the charger. 10 ISET In the MAX17015, when the adapter is absent, drive ISET above 1V to enable IINP during battery discharge. When the adapter is reinserted, ISET must be released to the correct control level within 300ms. 11 12 13 14 15 16 17 18 19 20 -- PGND DLO LDO BST DHI LX ACIN VAA CC VCTL BP Power Ground Connection for MOSFET Drivers Low-Side Power-MOSFET Driver Output. Connect to low-side n-channel MOSFET gate. Linear Regulator Output. LDO provides the power to the MOSFET drivers. LDO is the output of the 5.4V linear regulator supplied from DCIN. Bypass LDO with a 4.7F ceramic capacitor from LDO to PGND. High-Side Driver Supply. Connect a 0.68F capacitor from BST to LX. High-Side Power-MOSFET Driver Output. Connect to high-side n-channel MOSFET gate. High-Side Driver Source Connection. Connect a 0.68F capacitor from BST to LX. AC Adapter Detect Input. ACIN is the input to an uncommitted comparator. 4.2V Voltage Reference and Device Power-Supply Input. Bypass VAA with a 1F capacitor to GND. Voltage Regulation Loop-Compensation Point. Connect 3k and 0.01F capacitor in series from CC to GND. Battery Voltage Adjust Input. VCTL sets the number of cells and adjusts the voltage per cell. The adjustment range is 4.2V to 4.4V per cell. See the Setting Charge Voltage section. Backside Paddle. Connect the backside paddle to analog ground. FUNCTION Charger Bias Supply Input. Bypass DCIN with a 1F capacitor to PGND.
MAX17005/MAX17006/MAX17015
Dual Mode is a trademark of Maxim Integrated Products, Inc.
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1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
SYSTEM LOAD Q1a ADAPTER N3 R9 2M RACIN1 N4 BATT LDO 10k ACOK RACIN2 R1 22.6k C2 0.1F LX IINP DLO PGND CSIP VAA C3 1F R2 R3 VCTL BATT PWM SIGNAL ISET CC C5 0.01F LDO C1 4.7F ONLY FOR MAX17015 R5 3k R7 R8 GND N2 L1 DCIN ACIN DHI CSSP CSSN BST C4 0.68F N1 CIN = 2 x 4.7F COUT = 4.7F L1 = 2H C6 1F R4 200k C7 0.1F CIN RS1 15m Q1b
ADAPTER R6 200k
D1
MAX17005 MAX17006 MAX17015
RS2 10m CSIN COUT BATTERY
Figure 1. Typical Operating Circuit
Detailed Description
The MAX17005/MAX17006/MAX17015 include all the functions necessary to charge Li+, NiMH, and NiCd batteries. An all n-channel synchronous-rectified stepdown DC-DC converter is used to implement a precision constant-current, constant-voltage charger. The charge current and input current-limit sense amplifiers have low-input offset errors (250V typ), allowing the use of small-valued sense resistors.
10
The MAX17005/MAX17006/MAX17015 use a new thermally optimized high-frequency architecture. With this new architecture, the switching frequency is adjusted to control the power dissipation in the high-side MOSFET. Benefits of the new architecture include: reduced output capacitance and inductance, resulting in smaller printed-circuit board (PCB) area and lower cost.
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1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
IINP ACIN ACOK
CSSP CSA A = 17.5V/V CSSN Gm = 2.8A/mV VAA/2
LDO
BATT
DCIN 4.2V REFERENCE VAA
GMS VCTL + 100mV 60mV GND BDIV CC BATT CELL SELECT LOGIC 10mV BDIV GMV VCTL LOWEST VOLTAGE CLAMP POWER FAIL OVP IMIN
5.4V LINEAR REGULATOR
LDO
BST DC-DC CONVERTER CCMP LEVEL SHIFT HIGH-SIDE DRIVER DHI LX LDO
VAA
CSI
CSIP CSA A = 17.5V/V CSIN GMI 110mV IMAX IZX
LOW-SIDE DRIVER
DLO PGND
PWM FILTER
26mV CHARGER 10mV SHUTDOWN
ISET
MAX17005 MAX17006 MAX17015
Figure 2. Functional Diagram
The MAX17005/MAX17006/MAX17015 feature a voltage-regulation loop (CCV) and two current-regulation loops (CCI and CCS). The loops operate independently of each other. The CCV voltage-regulation loop monitors BATT to ensure that its voltage never exceeds the voltage set by VCTL. The CCI battery charge currentregulation loop monitors current delivered to BATT to ensure that it never exceeds the current limit set by ISET. The charge current-regulation loop is in control as long as the battery voltage is below the set point. When the battery voltage reaches its set point, the voltage-
regulation loop takes control and maintains the battery voltage at the set point. A third loop (CCS) takes control and reduces the charge current when the adapter current exceeds the input current limit. The MAX17005/MAX17006/MAX17015 have singlepoint compensation. The two current loops are internally compensated while the voltage loop is compensated with a series RC network at CC pin. See the CC Loop Compensation section for the resistor and capacitor selection. A functional diagram is shown in Figure 2.
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1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
Setting Charge Voltage
The VCTL input adjusts the battery-output voltage, VBATT, and determines the number of cells. For 3- and 4-cell applications, use the MAX17005; for 2- and 3-cell applications, use the MAX17006. Use the MAX17015 to adjust the cell number and set the cell voltage with a resistive voltage-divider from the output. Based on the version of the part, the number of cells and the level of VCTL should be set as in Table 1: There are two constraints in choosing R7 and R8. The resistors cannot be too small since they discharge the battery, and they cannot be too large because FB pin consumes less than 1A of input bias current. Pick R8 to be approximately 10k and then calculate R7. FB regulation error (0.5% max) and the tolerance of R7 and R8 both contribute to the error on the battery voltage. Use 0.1% feedback resistors for best accuracy.
Table 1. Cell Configuration
VERSION MAX17005 MAX17005 MAX17006 MAX17006 MAX17015 NO. OF CELLS 3 4 2 3 Sets FB LEVEL 2.4V < VCTL < 4.2V 0V < VCTL < 1.8V 0V < VCTL < 1.8V 2.4V < VCTL < 4.2V VCTL = GND or VCTL = VAA
Setting Charge Current
The voltage at ISET determines the voltage across current-sense resistor RS2. ISET can accept either analog or digital inputs. The full-scale differential voltage between CSIP and CSIN is 80mV (8A for RS2 = 10m) for the analog input, and 60mV (6A for RS2 = 10m) for the digital PWM input. When the MAX17005/MAX17006/MAX17015 power up and the charger is ready, if there is no clock edge within 20ms, the circuit assumes ISET is an analog input, and disables the PWM filter block. To configure the charge current, force the voltage on ISET according to the following equation: ICHG = 240mV VISET x RS2 VAA
The MAX17005 and MAX17006 support from 4.2V/cell to 4.4V/cell, whereas the MAX17015 supports minimum 2.1V. The maximum voltage is determined with the dropout performance of IC. When the required voltage falls outside the range available with the MAX17005 or MAX17006, the MAX17015 should be used. The charge-voltage regulation for the MAX17005 and MAX17006 is calculated with the following equations: VCELL = 4.2V + 4.2V - VVCTL 6
The input range for ISET is from 0 to VAA/2. To shut down the charger, pull ISET below 26mV. If there is a clock edge on ISET within 20ms, the PWM filter is enabled and ISET accepts digital PWM input. The PWM filter has a DAC with 8-bit resolution that corresponds to equivalent VCSIP-CSIN steps.
for 3-cell selection of MAX17005 and MAX17006, 4.2V > VCTL > 2.4V: V VCELL = 4.2V + VCTL 6 for 2- or 4-cell selection of MAX17006 or MAX17005, respectively, 0V < VCTL < 1.8V. Connect VCTL to GND or to VAA for default 4.2V/cell battery-voltage setting. For the MAX17015, connect VCTL to GND to set the FB regulation point to 2.1V. The charge-voltage regulation is calculated with the following equation: VCHG _ REG = VFB _ SETPOINT x R8 + R7 R8
Figure 3. MAX17015 Charge-Voltage Regulation Feedback Network
CSIN
COUT
MAX17015
FB
R7
BATTERY
R8
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1.2MHz Low-Cost, High-Performance Chargers
The PWM filter accepts the digital signal with a frequency from 128Hz to 500kHz. Zero duty cycle shuts down the MAX17005/MAX17006/MAX17015, and 99.5% duty cycle corresponds to full scale (60mV) across CSIP and CSIN. Choose a current-sense resistor (RS2) to have a sufficient power-dissipation rating to handle the full-charge current. The current-sense voltage can be reduced to minimize the power-dissipation period. However, this can degrade accuracy due to the current-sense amplifier's input offset (0.25mV typ). See Typical Operating Characteristics to estimate the charge-current accuracy at various set points.
MAX17005/MAX17006/MAX17015
IINPUT _ LIMIT =
60mV Rb x (1 + ) RS1 Ra
Setting Input-Current Limit
The total input current, from a wall adapter or other DC source, is the sum of the system supply current and the current required by the charger. When the input current exceeds the set input-current limit, the controller decreases the charge current to provide priority to system load current. System current normally fluctuates as portions of the system are powered up or down. The input-current-limit circuit reduces the power requirement of the AC wall adapter, which reduces adapter cost. As the system supply rises, the available charge current drops linearly to zero. Thereafter, the total input current can increase without limit. The total input current is the sum of the device supply current, the charger input current, and the system load current. The total input current can be estimated as follows: I x VBATTERY IINPUT = ILOAD + CHARGE VIN x where is the efficiency of the DC-to-DC converter (typically 85% to 95%). In the MAX17005/MAX17006/MAX17015, the voltage across CSSP and CSSN is constant at 60mV. Choose the current-sense resistor, RS1, to set the input current limit. For example, for 4A input current limit, choose RS1 = 15m. For the input current-limit settings, which cannot be achievable with standard sense resistor values, use a resistive voltage-divider between CSSP and CSSN to tune the setting (Figure 4).
RS1
To minimize power dissipation, first choose RS1 according to the closest available value. For convenience, choose Ra = 6k and calculate Rb from the above equation. Choose a current-sense resistor (RS1) to have a sufficient power rating to handle the full system current. The current-sense resistor can be reduced to improve efficiency, but this degrades accuracy due to the currentsense amplifier's input offset (0.15mV typ). See Typical Operating Characteristics to estimate the input currentlimit accuracy at various set points.
Automatic Power-Source Selection
The MAX17005/MAX17006/MAX17015 use an external charge pump to drive the gate of an n-channel adapter selection switch (N3 and Q1a). In Figure 1, when the adapter is present, BST is biased 5V above VADAPTER so that N3 and Q1a are on, and Q1b is off. As long as the adapter is present, even though the charger is off, the power stage forces a refresh pulse to the BST charge pump every 5ms. When the adapter voltage is removed, the charger stops generating BST refresh pulses and N4 forces N2 off, Q1b turns on and supplies power to the system from the battery. In Figure 1, D1 must have low forward-voltage drop and low reverse-leakage current to ensure sufficient gate drive at N3 and Q1a. A 100mA, low reverse-leakage Schottky diode is the right choice.
Analog Input Current-Monitor Output
Use IINP to monitor the system-input current, which is sensed across CSSP and CSSN. The voltage at IINP is proportional to the input current: IINPUT = VIINP RS1 x GIINP x RIINP
Rb Ra CSSP CSSN
where I INPUT is the DC current supplied by the AC adapter, GIINP is the transconductance of the sense amplifier (2.8 mA/V typ), and RIINP is the resistor connected between IINP and ground. Typically, IINP has a 0V to 3.5V output voltage range. Leave IINP unconnected when not used.
MAX17005/MAX17006/MAX17015 Figure 4. Input Current-Limit Fine Tuning
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1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
Operating Conditions
Q1a RS1 15m CIN C7 10nF ADAPTER Q1b R6 50k BATTERY D1 CSSP CSSN BST C4 0.1F SYSTEM LOAD
The MAX17005/MAX17006/MAX17015 have the following operating states: * Adapter Present: When DCIN is greater than 8.7V, the controller detects the adapter. In this condition, both the LDO and VAA turn on and battery charging is allowed: a) Charging: The total MAX17005/MAX17006/ MAX17015 quiescent current when charging is 3mA (max) plus the current required to drive the MOSFETs. b) Not Charging: To disable charging drive ISET below 26mV. When the adapter is present and charging is disabled, the total adapter quiescent current is less than 1.5mA and the total battery quiescent current is less than 60A. The charge pump still operates. * Adapter Absent (Power Fail): When VDCIN is less than VCSIN + 120mV, the DC-DC converter is in dropout. The charger detects the dropout condition and shuts down.
MAX17015
DHI LX N1
Figure 5. Current-Monitoring Design Battery Discharge
IINP can also be used to monitor battery discharge current (see Figure 5). In the MAX17015, when the adapter is absent, drive ISET above 1V to enable IINP during battery discharge. When the adapter is reinserted, ISET must be released to the correct control level within 300ms.
The MAX17005/MAX17006/MAX17015 allow charging under the following conditions: * DCIN > 7.5V, LDO > 4V, VAA > 3.1V * * VDCIN > VCSIN + 420mV (300mV falling hysteresis) VISET > 45mV or PWM detected
AC Adapter Detection
The MAX17005/MAX17006/MAX17015 include a hysteretic comparator that detects the presence of an AC power adapter. When ACIN is lower than 2.1V, the open-drain ACOK output becomes high impedance. Connect a 10k pullup resistance between LDO and ACOK. Use a resistive voltage-divider from the adapter's output to the ACIN pin to set the appropriate detection threshold. Select the resistive voltage-divider so that the voltage on ACIN does not to exceed its absolute maximum rating (6V).
____________________DC-DC Converter
The MAX17005/MAX17006/MAX17015 employ a synchronous step-down DC-DC converter with an n-channel high-side MOSFET switch and an n-channel low-side synchronous rectifier. The charger features a controlled inductor current-ripple architecture, currentmode control scheme with cycle-by-cycle current limit. The controller's off-time (tOFF) is adjusted to keep the high-side MOSFET junction temperature constant. In this way, the controller switches faster when the highside MOSFET has available thermal capacity. This allows the inductor current ripple and the output-voltage ripple to decrease so that smaller and cheaper components can be used. The controller can also operate in discontinuous conduction mode for improved light-load efficiency.
LDO Regulator and VAA An integrated low-dropout (LDO) linear regulator provides a 5.4V supply derived from DCIN, and delivers over 40mA of load current. Do not use the LDO to external loads greater than 10mA. The LDO powers the gate drivers of the n-channel MOSFETs. See the MOSFET Drivers section. Bypass LDO to PGND with a 4.7F ceramic capacitor. VAA is 4.2V reference supplied by DCIN. VAA biases most of the control circuitry, and should be bypassed to GND with a 1F or greater ceramic capacitor.
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BDIV OVP SET POINT + 100mV CSI IMAX 11A
R CCMP LVC
Q
DH DRIVER
IMIN S 1A Q DL DRIVER
ZCMP 1A OFF-TIME ONE SHOT OFF-TIME COMPUTE
CSSP CSIN
Figure 6. DC-DC Converter Functional Diagram
The operation of the DC-to-DC controller is determined by the following five comparators as shown in the functional diagram in Figures 2 and 6: * The IMIN comparator triggers a pulse in discontinuous mode when the accumulated error is too high. IMIN compares the control signal (LVC) against 10mV (referred at VCSIP - VCSIN). When LVC is less than this threshold, DHI and DLO are both forced low. Indirectly, IMIN sets the peak inductor current in discontinuous mode. * The CCMP comparator is used for current-mode regulation in continuous-conduction mode. CCMP compares LVC against the inductor current. The high-side MOSFET on-time is terminated when the CSI voltage is higher than LVC. The IMAX comparator provides a secondary cycleby-cycle current limit. IMAX compares CSI to 110mV (corresponding to 11A when RS2 = 10m).
The high-side MOSFET on-time is terminated when the current-sense signal exceeds 11A. A new cycle cannot start until the IMAX comparator's output goes low. * The ZCMP comparator provides zero-crossing detection during discontinuous conduction. ZCMP compares the current-sense feedback signal to 1A (RS2 = 10m). When the inductor current is lower than the 1A threshold, the comparator output is high, and DLO is turned off. * The OVP comparator is used to prevent overvoltage at the output due to battery removal. OVP compares BATT against the VCTL. When BATT is 100mV/cell above the set value, the OVP comparator output goes high, and the high-side MOSFET on-time is terminated. DHI and DLO remain off until the OVP condition is removed.
*
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1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
CC, CCI, CCS, and LVC Control Blocks
The MAX17005/MAX17006/MAX17015 control input current (CCS control loop), charge current (CCI control loop), or charge voltage (CC control loop), depending on the operating condition. The three control loops, CC, CCI, and CCS are brought together internally at the lowest voltage clamp (LVC) amplifier. The output of the LVC amplifier is the feedback control signal for the DC-DC controller. The minimum voltage at the CC, CCI, or CCS appears at the output of the LVC amplifier and clamps the other control loops to within 0.3V above the control point. Clamping the other two control loops close to the lowest control loop ensures fast transition with minimal overshoot when switching between different control loops (see the Compensation section). The CCS and CCI loops are compensated internally, and the CC loop is compensated externally. At the end of the computed off-time, the controller initiates a new cycle if the control point (LVC) is greater than 10mV (VCSIP - VCSIN referred), and the charge current is less than the cycle-by-cycle current limit. Restated another way, IMIN must be high, IMAX must be low, and OVP must be low for the controller to initiate a new cycle. If the peak inductor current exceeds IMAX comparator threshold or the output voltage exceeds the OVP threshold, then the on-time is terminated. The cycle-by-cycle current limit effectively protects against overcurrent and short-circuit faults. If during the off-time the inductor current goes to zero, the ZCMP comparator output pulls high, turning off the low-side MOSFET. Both the high- and low-side MOSFETs are turned off until another cycle is ready to begin. ZCOMP causes the MAX17005/MAX17006/ MAX17015 to enter into the discontinuous conduction mode (see the Discontinuous Conduction section).
Continuous-Conduction Mode
With sufficiently large charge current, the MAX17005/ MAX17006/MAX17015s' inductor current never crosses zero, which is defined as continuous-conduction mode. The controller starts a new cycle by turning on the highside MOSFET and turning off the low-side MOSFET. When the charge-current feedback signal (CSI) is greater than the control point (LVC), the CCMP comparator output goes high and the controller initiates the off-time by turning off the high-side MOSFET and turning on the low-side MOSFET. The operating frequency is governed by the off-time and is dependent upon VCSIN and VDCIN. The on-time can be determined using the following equation: L x IRIPPLE tON = VDCIN - VBATT where: V xt IRIPPLE = BATT OFF L The switching frequency can then be calculated: fSW = 1 tON + tOFF
Discontinuous Conduction
The MAX17005/MAX17006/MAX17015 can also operate in discontinuous conduction mode to ensure that the inductor current is always positive. The MAX17005/ MAX17006/MAX17015 enter discontinuous conduction mode when the output of the LVC control point falls below 10mV (referred at VCSIP - VCSIN). For RS2 = 10m, this corresponds to a peak inductor current of 1A. In discontinuous mode, a new cycle is not started until the LVC voltage rises above IMIN. Discontinuous mode operation can occur during conditioning charge of overdischarged battery packs, when the charge current has been reduced sufficiently by the CCS control loop, or when the charger is in constant-voltage mode with a nearly full battery pack.
Compensation
The charge voltage, charge current, and input currentlimit regulation loops are compensated separately. The charge current and input current-limit loops, CCI and CCS, are compensated internally, whereas the charge voltage loop is compensated externally at CC.
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CC Loop Compensation The simplified schematic in Figure 7 is sufficient to describe the operation of the controller's voltage loop, CC. The required compensation network is a pole-zero pair formed with CCC and RCC. The zero is necessary to compensate the pole formed by the output capacitor and the load. RESR is the equivalent series resistance (ESR) of the charger output capacitor (COUT). RL is the equivalent charger output load, where RL = VBATT/ ICHG. The equivalent output impedance of the GMV amplifier, ROGMV, is greater than 10M. The voltageamplifier transconductance, GMV = 0.125A/mV. The DC-DC converter transconductance is dependent upon charge current-sense resistor RS2:
MAX17005/MAX17006/MAX17015
GMOUT =
1 ACSI x RS2
where ACSI = 20, and RS2 = 10m in the typical application circuits, so GMOUT = 5A/V. The loop transfer function is given by: LTF = GMOUT x RL x GMV x ROGMV x (1 + sCOUT x RESR )(1 + sCCC x RCC ) (1 + sCCC x ROGMV )(1 + sCOUT x RL )
BATT GMOUT RESR RL COUT
The poles and zeros of the voltage-loop transfer function are listed from lowest frequency to highest frequency in Table 2. Near crossover, CCC is much lower impedance than ROGMV. Since CCC is in parallel with ROGMV, CCC dominates the parallel impedance near crossover. Additionally, RCC is much higher impedance than CCC and dominates the series combination of RCC and CCC, so: ROGMV x (1 + sCCC x RCC ) RCC (1 + sCCC x ROGMV ) C OUT is also much lower impedance than R L near crossover so the parallel impedance is mostly capacitive and: RL 1 (1 + sCOUT x RL ) sCOUT
CC GMV RCC ROGMV CCC VCTL
Figure 7. CC Loop Diagram
Table 2. CC Loop Poles and Zeros
NAME CCV Pole EQUATION DESCRIPTION Lowest frequency pole created by CCV and GMV's finite output resistance. Voltage-loop compensation zero. If this zero is at the same frequency or lower than output pole f P_OUT, the loop-transfer function approximates a single-pole response near the crossover frequency. Choose CCV to place this zero at least one decade below crossover to ensure adequate phase margin. Output pole formed with the effective load resistance RL and the output capacitance C OUT. RL influences the DC gain but does not affect the stability of the system or the crossover frequency. Output ESR Zero. This zero can keep the loop from crossing unity gain if f Z_OUT is less than the desired crossover frequency; therefore, choose a capacitor with an ESR zero greater than the crossover frequency.
fP _ CV =
1 2ROGMV x CCC 1 2RCC x CCC 1 2RL x COUT 1 2RESR x COUT
CCV Zero
fZ _ CV =
Output Pole Output Zero
fP _ OUT = fZ _ OUT =
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1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
If RESR is small enough, its associated output zero has a negligible effect near crossover and the loop-transferfunction can be simplified as follows: LTF = GMOUT x RCC G sCOUT MV Figure 8 shows the Bode plot of the voltage-loopfrequency response using the values calculated above.
MOSFET Drivers
The DHI and DLO outputs are optimized for driving moderate-sized power MOSFETs. The MOSFET drive capability is the same for both the low-side and highsides switches. This is consistent with the variable duty factor that occurs in the notebook computer environment where the battery voltage changes over a wide range. There must be a low-resistance, low-inductance path from the DLO driver to the MOSFET gate to prevent shoot-through. Otherwise, the sense circuitry in the MAX17005/MAX17006 interpret the MOSFET gate as "off" while there is still charge left on the gate. Use very short, wide traces measuring 10 to 20 squares or fewer (1.25mm to 2.5mm wide if the MOSFET is 25mm from the device). Unlike the DLO output, the DHI output uses a 50ns (typ) delay time to prevent the low-side MOSFET from turning on until DHI is fully off. The same considerations should be used for routing the DHI signal to the high-side MOSFET. The high-side driver (DHI) swings from LX to 5V above LX (BST) and has a typical impedance of 1.5 sourcing and 0.8 sinking. The strong high-side MOSFET driver eliminates most of the power dissipation due to switching losses. The low-side driver (DLO) swings from LDO to ground and has a typical impedance of 3 sinking and 3 sourcing. This helps prevent DLO from being pulled up when the high-side switch turns on due to capacitive coupling from the drain to the gate of the low-side MOSFET. This places some restrictions on the MOSFETs that can be used. Using a low-side MOSFET with smaller gate-to-drain capacitance can prevent these problems.
Setting LTF = 1 to solve for the unity-gain frequency yields: RCC fCO _ CV = GMOUT x GMV x 2 x COUT For stability, choose a crossover frequency lower than 1/10 the switching frequency (f OSC) . For example, choose a crossover frequency of 50kHz and solve for RCC using the component values listed in Figure 1 to yield RCC = 3k: RCC = 2 x COUT x fCO _ CV GMV x GMOUT 3k
GMV = 0.125A/mV GMOUT = 5A/V COUT = 4.7F fOSC_CV = 600kHz RL = 0.2 fCO_CV = 50kHz To ensure that the compensation zero adequately cancels the output pole, select fZ_CV fP_OUT: CCC (RL/RCC) x COUT C CC 300pF (assuming 2 cells and 2A maximum charge current).
80 60 40 20 0 -20 -40 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) MAG PHASE -135 1M -90 -45 PHASE (DEGREES) MAGNITUDE (dB) 0
Design Procedure
MOSFET Selection
Choose the n-channel MOSFETs according to the maximum required charge current. The MOSFETs must be able to dissipate the resistive losses plus the switching losses at both VDCIN(MIN) and VDCIN(MAX). For the high-side MOSFET, the worst-case resistive power losses occur at the maximum battery voltage and minimum supply voltage: PDCOND (HighSide) = VBATT(MAX) VDCIN(MIN) x ICHG2 x RDS(ON)
Figure 8. CC Loop Response
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Generally, a low gate charge high-side MOSFET is preferred to minimize switching losses. However, the RDS(ON) required to stay within package power dissipation often limits how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction losses. High-side switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in N1 due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including a verification using a thermocouple mounted on N1: 1 PDSW (HS) = x t TRANS x VCSSP x ICHG x fSW 2 where tTRANS is the drivers transition time and can be calculated as follows: 1 1 t TRANS = + x ( QGD + QGS ) IGSRC IGSNK IGSRC and IGSNK are the peak gate-drive source/sink current (3 sourcing and 0.8 sinking, typically). The MAX17005/MAX17006/MAX17015 control the switching frequency as shown in the Typical Operating Characteristics. The following is the power dissipated due to high-side n-channel MOSFET's output capacitance (CRSS): PDCRSS (HS) V 2CSSP x CRSS x fSW 2 Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied. If the high-side MOSFET chosen for adequate RDS(ON) at low-battery voltages becomes hot when biased from VDCIN(MAX), consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (N2), the worst-case power dissipation always occurs at maximum input voltage: VBATT(MIN) 2 PDCOND (LS) = 1 - x ICHG x RDS(ON) VCSSP(MAX) The following additional loss occurs in the low-side MOSFET due to the body diode conduction losses: PDBDY (LS) = 0.05 x IPEAK x 0.4V The total power low-side MOSFET dissipation is: PDTOTAL (LS) PDCOND (LS) + PDBDY (LS) These calculations provide an estimate and are not a substitute for breadboard evaluation, preferably including a verification using a thermocouple mounted on the MOSFET.
MAX17005/MAX17006/MAX17015
Inductor Selection
The selection of the inductor has multiple trade-offs between efficiency, transient response, size, and cost. Small inductance is cheap and small, and has a better transient response due to higher slew rate; however, the efficiency is lower because of higher RMS current. High inductance results in lower ripple so that the need of the output capacitors for output voltage ripple goes low. The MAX17005/MAX17006/MAX17015 combine all the inductor trade-offs in an optimum way by controlling switching frequency. High-frequency operation permits the use of a smaller and cheaper inductor, and consequently results in smaller output ripple and better transient response. The charge current, ripple, and operating frequency (off-time) determine the inductor characteristics. For optimum efficiency, choose the inductance according to the following equation: L= where k = 35ns/V. k x VIN2 4 x ICHG x LIRMAX
The following high-side MOSFET's loss is due to the reverse-recovery charge of the low-side MOSFET's body diode: PDQRR (HS) = QRR2 x VCSSP x fSW 2
Ignore PDQRR(HighSide) if a Schottky diode is used parallel to a low-side MOSFET. The total high-side MOSFET power dissipation is: PDTOTAL (HS) PDCOND (HS) + PDSW (HS) + PDCRSS (HS) + PDQRR (HS)
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1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
For optimum size and inductor current ripple, choose LIRMAX = 0.4, which sets the ripple current to 40% the charge current and results in a good balance between inductor size and efficiency. Higher inductor values decrease the ripple current. Smaller inductor values save cost but require higher saturation current capabilities and degrade efficiency. Inductor L1 must have a saturation current rating of at least the maximum charge current plus 1/2 the ripple current (IL): ISAT = ICHG + (1/2) IL The ripple current is determined by: IL = k x VIN2 4L Choose kCAP-BIAS is a derating factor of 2 for typical 25Vrated ceramic capacitors. For fSW = 800kHz, IRIPPLE = 1A, and to get VBATT = 70mV, choose COUT as 4.7F. If the internal resistance of battery is close to the ESR of the output capacitor, the voltage ripple is shared with the battery and is less than calculated.
Applications Information
Setting Input Current Limit
The input current limit should be set based on the current capability of the AC adapter and the tolerance of the input current limit. The upper limit of the input current threshold should never exceed the adapter's minimum available output current. For example, if the adapter's output current rating is 5A 10%, the input current limit should be selected so that its upper limit is less than 5A x 0.9 = 4.5A. Since the input current-limit accuracy of the MAX17005/MAX17006/MAX17015 is 3%, the typical value of the input current limit should be set at 4.5A/1.03 4.36A. The lower limit for input current must also be considered. For chargers at the low end of the spec, the input current limit for this example could be 4.36A x 0.95 or approximately 4.14A.
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. Nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resilience to powerup and surge currents: V BATT x ( VDCIN - VBATT ) IRMS = ICHG x VDCIN The input capacitors should be sized so that the temperature rise due to ripple current in continuous conduction does not exceed approximately 10C. The maximum ripple current occurs at 50% duty factor or VDCIN = 2 x VBATT, which equates to 0.5 x ICHG. If the application of interest does not achieve the maximum value, size the input capacitors according to the worstcase conditions.
Layout and Bypassing
Bypass DCIN with a 0.1F ceramic to ground (Figure 1). N1 and N2 protect the MAX17005/MAX17006/ MAX17015 when the DC power source input is reversed. Bypass VAA, CSSP, and LDO as shown in Figure 1. Good PCB layout is required to achieve specified noise immunity, efficiency, and stable performance. The PCB layout designer must be given explicit instructions-- preferably, a sketch showing the placement of the power switching components and high current routing. Refer to the PCB layout in the MAX17005/MAX17006/ MAX17015 evaluation kit for examples. A ground plane is essential for optimum performance. In most applications, the circuit is located on a multilayer board, and full use of the four or more copper layers is recommended. Use the top layer for high-current connections, the bottom layer for quiet connections, and the inner layers for an uninterrupted ground plane. Use the following step-by-step guide: 1) Place the high-power connections first, with their grounds adjacent: a) Minimize the current-sense resistor trace lengths, and ensure accurate current sensing with Kelvin connections. b) Minimize ground trace lengths in the high-current paths.
Output Capacitor Selection
The output capacitor absorbs the inductor ripple current and must tolerate the surge current delivered from the battery when it is initially plugged into the charger. As such, both capacitance and ESR are important parameters in specifying the output capacitor as a filter and to ensure the stability of the DC-to-DC converter (see the Compensation section.) Beyond the stability requirements, it is often sufficient to make sure that the output capacitor's ESR is much lower than the battery's ESR. Either tantalum or ceramic capacitors can be used on the output. Ceramic devices are preferable because of their good voltage ratings and resilience to surge currents. Choose the output capacitor based on: COUT = IRIPPLE x kCAP - BIAS fSW x 8 x VBATT
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c) Minimize other trace lengths in the high-current paths. d) Use > 5mm wide traces in the high-current paths. e) Connect CIN to high-side MOSFET (10mm max length). f) Minimize the LX node (MOSFETs, rectifier cathode, inductor (15mm max length)). Keep LX on one side of the PCB to reduce EMI radiation. Ideally, surface-mount power components are flush against one another with their ground terminals almost touching. These high-current grounds are then connected to each other with a wide, filled zone of top-layer copper, so they do not go through vias. The resulting top-layer subground plane is connected to the normal inner-layer ground plane at the paddle. Other high-current paths should also be minimized, but focusing primarily on short ground and current-sense connections eliminates about 90% of all PCB layout problems. 2) Place the IC and signal components. Keep the main switching node (LX node) away from sensitive analog components (current-sense traces and VAA capacitor). Important: the IC must be no further than 10mm from the current-sense resistors. Quiet connections to VAA and CC should be returned to a separate ground (GND) island. There is very little current flowing in these traces, so the ground island need not be very large. When placed on an inner layer, a sizable ground island can help simplify the layout because the low-current connections can be made through vias. The ground pad on the backside of the package should also be connected to this quiet ground island. 3) Keep the gate drive traces (DHI and DLO) as short as possible (L < 20mm), and route them away from the current-sense lines and V AA . These traces should also be relatively wide (W > 1.25mm). 4) Place ceramic bypass capacitors close to the IC. The bulk capacitors can be placed further away. Place the current-sense input filter capacitors under the part, connected directly to the GND pin. 5) Use a single-point star ground placed directly below the part at the PGND pin. Connect the power ground (ground plane) and the quiet ground island at this location.
MAX17005/MAX17006/MAX17015
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1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
Minimal Operating Circuit
ADAPTER SYSTEM
ADAPTER DCIN BATT LDO DHI LX DLO VAA PGND GND CSSP CSSN BST
IINP
MAX17005 MAX17006 MAX17015
CSIP
CSIN
BATTERY
VCTL
BATT CC
ISET ACOK ACIN
Pin Configuration
LDO PGND DLO BST DHI
Chip Information
TRANSISTOR COUNT: 12,990 PROCESS: BiCMOS
TOP VIEW
15 LX 16 ACIN 17 VAA 18 CC 19 VCTL 20 1 DCIN
14
13
12
11 10 9 ISET CSSN CSSP ACOK BATT
MAX17005 MAX17006 MAX17015
EXPOSED PADDLE
8 7 6 5 IINP
2 AGND
3 CSIP
4 CSIN
THIN QFN 4mm x 4mm
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1.2MHz Low-Cost, High-Performance Chargers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
MAX17005/MAX17006/MAX17015
______________________________________________________________________________________
23
1.2MHz Low-Cost, High-Performance Chargers MAX17005/MAX17006/MAX17015
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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